MC68HC711D3CFNE2 Datasheet, PDF (30/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
Table 3-2 Instruction Set (Sheet 3 of 7)
Mnemonic Operation
Description
Addressing
Instruction
Condition Codes
Mode
Opcode Operand Cycles S X H I N Z V C
CLRA
Clear
Accumulator A
0⇒A
A
INH
4F
—
2
———— 0 1 0 0
CLRB
Clear
0⇒B
B
INH
5F
—
2
———— 0 1 0 0
Accumulator B
CLV
Clear Overflow
Flag
0⇒V
INH
0A
—
2
—————— 0 —
CMPA (opr) Compare A to
Memory
A–M
A
IMM
A
DIR
81 ii
91 dd
2
———— ∆ ∆ ∆ ∆
3
A
EXT
B1 hh ll
4
A
IND,X
A1 ff
4
A
IND,Y 18
A1 ff
5
CMPB (opr) Compare B to
B–M
B
IMM
C1 ii
2
———— ∆ ∆ ∆ ∆
Memory
B
DIR
B
EXT
D1 dd
3
F1 hh ll
4
B
IND,X
E1 ff
4
B
IND,Y 18
E1 ff
5
COM (opr)
Ones
Complement
$FF – M ⇒ M
EXT
IND,X
73 hh ll
63 ff
6
———— ∆ ∆ 0 1
6
Memory Byte
IND,Y 18
63 ff
7
COMA
Ones
$FF – A ⇒ A A
INH
Complement
43
—
2
———— ∆ ∆ 0 1
A
COMB
Ones
$FF – B ⇒ B B
INH
Complement
53
—
2
———— ∆ ∆ 0 1
B
CPD (opr) Compare D to D – M : M + 1
IMM 1A 83 jj kk
5
———— ∆ ∆ ∆ ∆
Memory 16-Bit
DIR
1A 93 dd
6
EXT 1A B3 hh ll
7
IND,X 1A A3 ff
7
IND,Y CD A3 ff
7
CPX (opr) Compare X to IX – M : M + 1
IMM
Memory 16-Bit
DIR
8C jj kk
9C dd
4
———— ∆ ∆ ∆ ∆
5
EXT
BC hh ll
6
IND,X
AC ff
6
IND,Y CD AC ff
7
CPY (opr) Compare Y to
Memory 16-Bit
IY – M : M + 1
IMM
18
8C jj kk
DIR
18
9C dd
5
———— ∆ ∆ ∆ ∆
6
EXT
18
BC hh ll
7
IND,X 1A AC ff
7
IND,Y 18
AC ff
7
DAA
Decimal Adjust Adjust Sum to BCD
INH
A
19
—
2
———— ∆ ∆ ∆ ∆
DEC (opr) Decrement
Memory Byte
M–1⇒M
EXT
IND,X
7A hh ll
6A ff
6
———— ∆ ∆ ∆ —
6
IND,Y 18
6A ff
7
DECA
Decrement
Accumulator
A–1⇒A
A
INH
4A
—
2
———— ∆ ∆ ∆ —
A
DECB
Decrement
Accumulator
B–1⇒B
B
INH
5A
—
2
———— ∆ ∆ ∆ —
B
DES
Decrement
SP – 1 ⇒ SP
INH
Stack Pointer
34
—
3
————————
DEX
Decrement
IX – 1 ⇒ IX
INH
09
—
3
————— ∆ ——
Index Register
X
DEY
Decrement
Index Register
IY – 1 ⇒ IY
INH
18
09
—
4
————— ∆ ——
Y
EORA (opr) Exclusive OR
A⊕M⇒A
A
IMM
A with Memory
A
DIR
88 ii
98 dd
2
———— ∆ ∆ 0 —
3
A
EXT
B8 hh ll
4
A
IND,X
A8 ff
4
A
IND,Y 18
A8 ff
5
EORB (opr) Exclusive OR
B⊕M⇒B
B
IMM
C8 ii
2
———— ∆ ∆ 0 —
B with Memory
B
DIR
B
EXT
D8 dd
3
F8 hh ll
4
B
IND,X
E8 ff
4
B
IND,Y 18
E8 ff
5
FDIV
Fractional D / IX ⇒ IX; r ⇒ D
INH
Divide 16 by
03
—
41 — — — — — ∆ ∆ ∆
16
IDIV
Integer Divide D / IX ⇒ IX; r ⇒ D
INH
16 by 16
02
—
41 — — — — — ∆ 0 ∆
3-10
CENTRAL PROCESSING UNIT
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