MC68HC711D3CFNE2 Datasheet, PDF (69/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
recovery scheme distinguishes valid data from noise in the serial data stream. The
data input is selectively sampled to detect receive data, and a majority voting circuit
determines the value and integrity of each bit.
RECEIVER
BAUD RATE
CLOCK
PD0
RxD
DDD0
÷16
PIN BUFFER
AND CONTROL
DATA
RECOVERY
DISABLE
DRIVER
RE
10 (11) - BIT
Rx SHIFT REGISTER
(8) 7 6 5 4 3 2 1 0
MSB
ALL ONES
M
WAKEUP
LOGIC
RWU
8
SCCR1 SCI CONTROL 1
SCSR SCI STATUS 1
RDRF
RIE
IDLE
ILIE
OR
RIE
SCDR Rx BUFFER
(READ ONLY)
8
8
SCCR2 SCI CONTROL 2
SCI Tx
REQUESTS
SCI INTERRUPT
REQUEST
TECHNICAL DATA
Figure 7-2 SCI Receiver Block Diagram
SERIAL COMMUNICATIONS INTERFACE
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INTERNAL
DATA BUS
11 SCI RX BLOCK
7-3