MC68HC711D3CFNE2 Datasheet, PDF (102/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
1
INTERRUPT
REQUESTS
2
TMSK2
E ÷ 64 CLOCK
(FROM MAIN TIMER)
PA7/
PAI/OC1
INPUT BUFFER
&
EDGE DETECTION
FROM
MAIN TIMER
OC1
OUTPUT
BUFFER
PAI EDGE
TFLG2
DISABLE
FLAG SETTING
2:1
MUX
OVERFLOW
ENABLE
PACNT
8-BIT COUNTER
PAEN
PACTL
INTERNAL
DATA BUS
Figure 9-3 Pulse Accumulator
11 PULSE ACC BLOCK
Table 9-3 Pulse Accumulator Timing
Selected Crystal
CPU Clock
(E)
Cycle Time
(1/E)
Pulse Accumulator (in Gated Mode)
(E/2⁶)
(E/2¹⁴)
1 count -
overflow -
Common XTAL Frequencies
4.0 MHz
1.0 MHz
1000 ns
8.0 MHz
2.0 MHz
500 ns
12.0 MHz
3.0 MHz
333 ns
64.0 µs
16.384 ms
32.0 µs
8.192 ms
21.33 µs
5.461 ms
Pulse accumulator control bits are also located within two timer registers, TMSK2 and
TFLG2, as described in the following paragraphs.
9-16
TIMING SYSTEM
For More Information On This Product,
Go to: www.freescale.com
TECHNICAL DATA