MC68HC711D3CFNE2 Datasheet, PDF (72/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes

Freescale Semiconductor, Inc.
T8 — Transmit Data bit 8
If M bit is set, T8 stores ninth bit in transmit data character.
M — Mode (Select Character Format)
0 = Start bit, 8 data bits, 1 stop bit
1 = Start bit, 9 data bits, 1 stop bit
WAKE — Wake-up by Address Mark/Idle
0 = Wake-up by IDLE line recognition
1 = Wake-up by address mark (most significant data bit set)
7.6.3 Serial Communications Control Register 2 (SCCR2)
The SCCR2 register provides the control bits that enable or disable individual SCI
functions.
SCCR2 — SCI Control Register 2
$002D
Bit 7
6
5
4
3
TIE
TCIE
RIE
ILIE
TE
RESET:
0
0
0
0
0
2
1
Bit 0
RE
RWU
SBK
0
0
0
TIE — Transmit Interrupt Enable
0 = TDRE interrupts disabled
1 = SCI interrupt requested when TDRE status flag is set
TCIE — Transmit Complete Interrupt Enable
0 = TC interrupts disabled
1 = SCI interrupt requested when TC status flag is set
RIE — Receiver Interrupt Enable
0 = RDRF and OR interrupts disabled
1 = SCI interrupt requested when RDRF flag or the OR status flag is set
ILIE — Idle Line Interrupt Enable
0 = IDLE interrupts disabled
1 = SCI interrupt requested when IDLE status flag is set
TE — Transmitter Enable
When TE goes from zero to one, one unit of idle character time (logic one) is queued
as a preamble.
0 = Transmitter disabled
1 = Transmitter enabled
RE — Receiver Enable
0 = Receiver disabled
1 = Receiver enabled
RWU — Receiver Wake-Up Control
0 = Normal SCI receiver
1 = Wake-up enabled and receiver interrupts inhibited
SERIAL COMMUNICATIONS INTERFACE
7-6
TECHNICAL DATA
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