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MC68HC711D3CFNE2 Datasheet, PDF (14/124 Pages) Freescale Semiconductor, Inc – Power Saving STOP and WAIT Modes
Freescale Semiconductor, Inc.
VSS
PC0/ADDR0
PC1/ADDR1
PC2/ADDR2
PC3/ADDR3
PC4/ADDR4
PC5/ADDR5
PC6/ADDR6
PC7/ADDR7
XIRQ/VPP
PD7/R/W
PD6/AS
RESET
IRQ
PD0/RxD
PD1/TxD
PD2/MISO
PD3/MOSI
PD4/SCK
PD5/SS
1
40 XTAL
2
39 EXTAL
3
38 E
4
37 MODA/LIR
5
36 MODB/VSTBY
6
35 PB0/ADDR8
7
34 PB1/ADDR9
8 MC68HC(7)11D3 33 PB2/ADDR10
9
32 PB3/ADDR11
10
31 PB4/ADDR12
11
30 PB5/ADDR13
12
29 PB6/ADDR14
13
28 PB7/ADDR15
14
27 PA0/IC3
15
26 PA1/IC2
16
25 PA2/IC1
17
24 PA3/IC4/OC5/OC1
18
23 PA5/OC3/OC1
19
22 PA7/PAI/OC1
20
21 VDD
D3 40-PIN DIP
Figure 2-2 Pin Assignments for 40-Pin DIP
2.1 VDD, VSS, and EVSS
Power is supplied to the MCU through VDD and VSS. VSS is the power supply, and
VSS is ground. EVSS, available on the 44-pin PLCC, is an additional ground pin that
must be grounded with VSS. The MCU operates from a single 5-volt (nominal) power
supply. Very fast signal transitions occur on the MCU pins. The short rise and fall times
place high, short duration current demands on the power supply. To prevent noise
problems, provide good power supply bypassing at the MCU. Also, use bypass capac-
itors that have good high-frequency characteristics and situate them as close to the
MCU as possible. Bypass requirements vary, depending on how heavily the MCU pins
are loaded.
2.2 Reset (RESET)
An active low bidirectional control signal, RESET, acts as an input to initialize the MCU
to a known startup state. It also acts as an open-drain output to indicate that an internal
failure has been detected in either the clock monitor or COP watchdog circuit. The
CPU distinguishes between internal and external reset conditions by sensing whether
the reset pin rises to a logic one in less than two E-clock cycles after a reset has oc-
curred. It is not advisable to connect an external resistor-capacitor (RC) power-up de-
lay circuit to the reset pin of M68HC11 devices because the circuit charge time
PIN DESCRIPTIONS
2-2
TECHNICAL DATA
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