MC68HC705C9A_1 Datasheet, PDF (96/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification _{SCI I/O Registers}
FE — Receiver Framing Error
This clearable, read-only flag is set when there is a logic zero where
a stop bit should be in the character shifted into the receive shift
register. If the received word causes both a framing error and an
overrun error, the OR flag is set and the FE flag is not set. Clear the
FE bit by reading the SCSR and then reading the SCDR.
1 = Framing error
0 = No framing error
9.14.5 Baud Rate Register (BAUD)
The baud rate register, shown in Figure 9-12, selects the baud rate for
both the receiver and the transmitter.
$000D
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
SCP1 SCP0
SCR2 SCR1
—
—
0
0
—
U
U
= Unimplemented U = Undetermined
Figure 9-12. Baud Rate Register (BAUD)
Bit 0
SCR0
U
SCP1 — SCP0–SCI Prescaler Select Bits
These read/write bits control prescaling of the baud rate generator
clock, as shown in Table 9-1. Reset clears both SCP1 and SCP0.
Table 9-1. Baud Rate Generator
Clock Prescaling
SCP[1:0]
00
01
10
11
Baud Rate Generator Clock
Internal Clock ÷ 1
Internal Clock ÷ 3
Internal Clock ÷ 4
Internal Clock ÷ 13
MC68HC705C9A — Rev. 2.0
Serial Communications Interface (SCI)
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