MC68HC705C9A_1 Datasheet, PDF (54/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification _{Computer Operating Properly (COP) Reset}
5.5 Computer Operating Properly (COP) Reset
This device includes a watchdog COP feature which guards against
program run-away failures. A timeout of the computer operating properly
(COP) timer generates a COP reset. The COP watchdog is a software
error detection system that automatically times out and resets the MCU
if not cleared periodically by a program sequence.
This device includes two COP types, one for C12A compatibility and the
other for C9A compatibility. When configured as a C9A the COP can be
enabled by user software by setting COPE in the C9A COP control
register (C9ACOPCR). When configured as a C12A, the COP is enabled
prior to operation by programming the C12COPE bit in the C12A mask
option register (C12MOR). The function and control of both COPs is
detailed below.
5.6 MC68HC05C9A Compatible COP
This COP is controlled with two registers; one to reset the COP timer and
the other to enable and control COP and clock monitor functions. Figure
5-3 shows a block diagram of the MC68HC05C9A COP.
CM1
INTERNAL
CPU
÷4 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2
CM0
CLOCK
16 BIT TIMER SYSTEM
2¹⁵
2¹³
2¹⁷
2¹⁹
COP
÷4
÷2 ÷2
÷2 ÷2
÷2 ÷2 ²²¹
COPRST
Figure 5-3. C9A COP Block Diagram
MC68HC705C9A — Rev. 2.0
Resets
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