MC68HC705C9A_1 Datasheet, PDF (74/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification _{Timer I/O Registers}
8.4.4 Alternate Timer Registers (ATRH and ATRL)
The alternate timer registers, shown in Figure 8-5, contain the current
high and low bytes of the 16-bit counter. Reading ATRH before reading
ATRL causes ATRL to be latched until ATRL is read. Reading ATRL has
no effect on the timer overflow flag (TOF). Writing to the alternate timer
registers has no effect.
ATRH
$001A
Read:
Write:
Reset:
Bit 7
BIT15
1
6
BIT14
1
5
BIT13
1
4
BIT12
1
3
BIT11
1
2
BIT10
1
1
BIT9
1
Bit 0
BIT8
1
ATRL
$001B
Read:
Write:
Reset:
Bit 7
BIT7
1
6
BIT6
5
BIT5
1
1
= Unimplemented
4
BIT4
1
3
BIT3
1
2
BIT2
1
1
BIT1
0
Bit 0
BIT0
0
Figure 8-5. Alternate Timer Registers (ATRH and ATRL)
NOTE:
To prevent interrupts from occurring between readings of ATRH and
ATRL, set the interrupt flag in the condition code register before reading
ATRH, and clear the flag after reading ATRL.
MC68HC705C9A — Rev. 2.0
Capture/Compare Timer
For More Information On This Product,
Go to: www.freescale.com