MC68HC705C9A_1 Datasheet, PDF (101/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification
SPI Signal Description
SS
SCK
SCK
SCK
SCK
MISO/MOSI
MSB
6
5
4
3
2
1
0
INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)
Figure 10-1. Data Clock Timing Diagram
CPOL = 0
CPHA = 0
CPOL = 0
CPHA = 1
CPOL = 1
CPHA = 0
CPOL = 1
CPHA = 1
10.4.1 Master In Slave Out (MISO)
The MISO line is configured as an input in a master device and as an
output in a slave device. It is one of the two lines that transfer serial data
in one direction, with the most significant bit sent first. The MISO line of
a slave device is placed in the high-impedance state if the slave is not
selected.
10.4.2 Master Out Slave In (MOSI)
The MOSI line is configured as an output in a master device and as an
input in a slave device. It is one of the two lines that transfer serial data
in one direction with the most significant bit sent first.
MC68HC705C9A — Rev. 2.0
Serial Peripheral Interface
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