MC68HC705C9A_1 Datasheet, PDF (75/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification
Timer I/O Registers
8.4.5 Input Capture Registers (ICRH and ICRL)
When a selected edge occurs on the TCAP pin, the current high and low
bytes of the 16-bit counter are latched into the input capture registers.
Reading ICRH before reading ICRL inhibits further capture until ICRL is
read. Reading ICRL after reading the status register clears the input
capture flag (ICF). Writing to the input capture registers has no effect.
ICRH
$0014
Read:
Write:
Bit 7
BIT15
6
BIT14
5
BIT13
4
BIT12
3
BIT11
2
BIT10
1
BIT9
Bit 0
BIT8
ICRL
$0015
Read:
Write:
Bit 7
BIT7
6
BIT6
5
BIT5
4
BIT4
3
BIT3
2
BIT2
1
BIT1
Bit 0
BIT0
RESET DOES NOT AFFECT THE INPUT CAPTURE REGISTERS
= Unimplemented
Figure 8-6. Input Capture Registers (ICRH and ICRL)
NOTE:
To prevent interrupts from occurring between readings of ICRH and
ICRL, set the interrupt flag in the condition code register before reading
ICRH, and clear the flag after reading ICRL.
MC68HC705C9A — Rev. 2.0
Capture/Compare Timer
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