MC68HC705C9A_1 Datasheet, PDF (107/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification
SPI Registers
Table 10-1. SPI Clock
Rate Selection
SPR[1:0] SPI Clock Rate
00
Internal Clock ÷ 2
01
Internal Clock ÷ 4
10
Internal Clock ÷ 16
11
Internal Clock ÷ 32
10.6.2 Serial Peripheral Status Register (SPSR)
The SPI status register, shown in Figure 10-5, contains flags to signal
the following conditions:
• SPI transmission complete
• Write collision
• Mode fault
SPSR
Read:
Write:
Reset:
Bit 7
SPIF
0
6
5
4
3
2
WCOL
0
MODF
0
0
0
0
0
0
0
= Unimplemented
Figure 10-5. SPI Status Register
1
Bit 0
0
0
0
0
SPIF — SPI Transfer Complete Flag
The serial peripheral data transfer flag bit is set upon completion of
data transfer between the processor and external device. If SPIF
goes high, and if SPIE is set, a serial peripheral interrupt is generated.
Clearing the SPIF bit is accomplished by reading the SPSR (with
SPIF set) followed by an access of the SPDR. Following the initial
transfer, unless SPSR is read (with SPIF set) first, attempts to write to
SPDR are inhibited.
MC68HC705C9A — Rev. 2.0
Serial Peripheral Interface
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