MC68HC705C9A_1 Datasheet, PDF (103/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification
Functional Description
10.5 Functional Description
Figure 10-2 shows a block diagram of the serial peripheral interface
circuitry. When a master device transmits data to a slave via the MOSI
line, the slave device responds by sending data to the master device via
the master’s MISO line. This implies full duplex transmission with both
data out and data in synchronized with the same clock signal. Thus, the
byte transmitted is replaced by the byte received and eliminates the
need for separate transmit-empty and receive-full status bits. A single
status bit (SPIF) is used to signify that the I/O operation has been
completed.
SPI SHIFT REGISTER
76543210
S
M
PD2/
MISO
M
PD3/
S MOSI
INTERNAL DATA BUS
SPDR ($000C)
INTERNAL
CLOCK
(XTAL ÷2)
SPIE
SPE
MSTR
SPIF
WCOL
MODF
DIVIDER
÷ 2 ÷ 4 ÷ 16 ÷ 32
SPI
CONTROL
SPI INTERRUPT REQUEST
SELECT
SPI CLOCK (MASTER)
SPR1 SPR0
CLOCK
LOGIC
MSTR CPHA CPOL
SPI
CLOCK
(SLAVE)
SPI
CLOCK
(MASTER)
PD5/
SS
PD4/
SCK
7
SPI CONTROL REGISTER (SPCR) SPIE
SPI STATUS REGISTER (SPSR) SPIF
SPI DATA REGISTER (SPDR) BIT 7
6
SPE
WCOL
BIT 6
5
DWOM
0
BIT 5
4
MSTR
MODF
BIT 4
3
CPOL
0
BIT 3
2
CPHA
0
BIT 2
1
SPR1
0
BIT 1
0
SPR2
0
BIT 0
$000A
$000B
$000C
Figure 10-2. Serial Peripheral Interface Block Diagram
MC68HC705C9A — Rev. 2.0
Serial Peripheral Interface
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