MC68HC705C9A_1 Datasheet, PDF (68/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification _{Timer Operation}
INTERNAL BUS
HIGH LOW
BYTE BYTE
INTERNAL
PROCESSOR
CLOCK
8-BIT
BUFFER
$16 OUTPUT
$17 COMPARE
REGISTER
÷4
HIGH
BYTE
LOW
BYTE
16-BIT FREE
RUNNING
$18
$19
COUNTER
COUNTER
ALTERNATE
REGISTER
$1A
$1B
HIGH LOW
BYTE BYTE
INPUT
CAPTURE
REGISTER
$14
$15
OUTPUT
COMPARE
CIRCUIT
OVERFLOW
DETECT
CIRCUIT
EDGE
DETECT
CIRCUIT
TIMER
STATUS
REG.
ICF OCF
TOF
$13
INTERRUPT CIRCUIT
DQ
OUTPUT ^CLK
LEVEL
REG. C
TIMER
ICIE
OCIE
TOIE
IEDG OLVL
CONTROLRESET
REG.
$12
OUTPUT EDGE
LEVEL INPUT
(TCMP) (TCAP)
Figure 8-1. Capture/Compare Timer Block Diagram
8.3 Timer Operation
The core of the capture/compare timer is a 16-bit free-running counter.
The counter provides the timing reference for the input capture and
output compare functions. The input capture and output compare
functions provide a means to latch the times at which external events
occur, to measure input waveforms, and to generate output waveforms
and timing delays. Software can read the value in the 16-bit free-running
counter at any time without affecting the counter sequence.
Because of the 16-bit timer architecture, the I/O registers for the input
capture and output compare functions are pairs of 8-bit registers.
MC68HC705C9A — Rev. 2.0
Capture/Compare Timer
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