MC68HC705C9A_1 Datasheet, PDF (57/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification
MC68HC05C9A Compatible COP
COPE — COP Enable
This bit is readable any time. COPE, CM1, and CM0 together may be
written with a single write, only once, after reset. This bit is cleared by
reset.
1 = COP enabled
0 = COP disabled
CM1 — COP Mode Bit 1
Used in conjunction with CM0 to establish the COP timeout period,
this bit is readable any time. COPE, CM1, and CM0 together may be
written with a single write, only once, after reset. This bit is cleared by
reset.
CM0 — COP Mode Bit 0
Used in conjunction with CM1 to establish the COP timeout period,
this bit is readable any time. COPE, CM1, and CM0 together may be
written with a single write, only once, after reset. This bit is cleared by
reset.
Bits 7–5 — Not Used
These bits always read as zero.
Table 5-1. COP Timeout Period
CM1 CM0
0
0
0
1
1
0
1
1
f_op/2¹⁵ Divide By
1
4
16
64
Timeout Period
(f_osc = 2.0 MHz)
32.77 ms
131.07 ms
524.29 ms
2.097 sec
Timeout Period
(f_osc = 4.0 MHz)
16.38 ms
65.54 ms
262.14 ms
1.048 sec
MC68HC705C9A — Rev. 2.0
Resets
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