MC68HC705C9A_1 Datasheet, PDF (94/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification _{SCI I/O Registers}
9.14.4 SCI Status Register (SCSR)
The SCI status register, shown in Figure 9-11, contains flags to signal
the following conditions:
• Transfer of SCDR data to transmit shift register complete
• Transmission complete
• Transfer of receive shift register data SCDR complete
• Receiver input idle
• Noisy data
• Framing error
$0010 Bit 7
6
5
4
3
2
1
Bit 0
Read:
TDRE
TC
RDRF IDLE
OR
NF
FE
Write:
Reset: 1
1
0
0
0
0
0
—
= Unimplemented
Figure 9-11. SCI Status Register (SCSR)
TDRE — Transmit Data Register Empty
This clearable, read-only flag is set when the data in the SCDR
transfers to the transmit shift register. TDRE generates an interrupt
request if the TIE bit in SCCR2 is also set. Clear the TDRE bit by
reading the SCSR with TDRE set and then writing to the SCDR. Reset
sets the TDRE bit. Software must initialize the TDRE bit to logic zero
to avoid an instant interrupt request when turning the transmitter on.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
TC — Transmission Complete
This clearable, read-only flag is set when the TDRE bit is set, and no
data, preamble, or break character is being transmitted. TDRE
generates an interrupt request if the TCIE bit in SCCR2 is also set.
Clear the TC bit by reading the SCSR with TC set, and then writing to
MC68HC705C9A — Rev. 2.0
Serial Communications Interface (SCI)
For More Information On This Product,
Go to: www.freescale.com