MC68HC705C9A_1 Datasheet, PDF (139/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification
Control Timing
IRQ PIN
t_ILIL
t_ILIH
a. Edge-Sensitive Trigger Condition. The minimum pulse width (t_ILIH) is either 125 ns (f_OP = 2.1 MHz)
or 250 ns (f_OP = 1 MHz). The period t_ILIL should not be less than the number of t_CYC cycles it takes to
execute the interrupt service routine plus 19 t_CYC cycles.
IR.Q1
t_ILIH
NORMALLY
USED WITH
.
.
WIRED-OR
IRQN
CONNECTION
IRQ
(INTERNAL)
b. Level-Sensitive Trigger Condition. If after servicing an interrupt the IRQ remains low,
the next interrupt is recognized
Figure 12-5. External Interrupt Timing
OSC¹
t_RL
RESET
t_ILIH
IRQ²
IRQ³
4064 t_CYC
INTERNAL
CLOCK
3FFE
3FFE
3FFE
3FFE
3FFE
3FFF4
NOTES:
1. Represents the internal clocking of the OSC1 pin
2. IRQ pin edge-sensitive mask option
3. IRQ pin level- and edge-sensitive mask option
4. RESET vector address shown for timing example
RESET OR INTERRUPT
VECTOR FETCH
Figure 12-6. STOP Recovery Timing Diagram
MC68HC705C9A — Rev. 2.0
Electrical Specifications
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