MC68HC705C9A_1 Datasheet, PDF (12/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification
Figure
Title
Page
7-1
Port A I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7-2
Port B I/O Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8-1
Capture/Compare Timer Block Diagram . . . . . . . . . . . . . . 68
8-2
Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . 70
8-3
Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . 72
8-4
Timer Registers (TRH and TRL) . . . . . . . . . . . . . . . . . . . . 73
8-5
Alternate Timer Registers (ATRH and ATRL) . . . . . . . . . . 74
8-6
Input Capture Registers (ICRH and ICRL) . . . . . . . . . . . . . 75
8-7
Output Compare Registers (OCRH and OCRL). . . . . . . . . 76
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
Serial Communications Interface Block Diagram . . . . . . . . 81
Rate Generator Division . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SCI Examples of Start Bit Sampling Techniques . . . . . . . . 87
SCI Sampling Technique Used on All Bits . . . . . . . . . . . . . 87
SCI Artificial Start Following a Frame Error . . . . . . . . . . . . 89
SCI Start Bit Following a Break . . . . . . . . . . . . . . . . . . . . . 89
SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . 90
SCI Control Register 1 (SCCR1) . . . . . . . . . . . . . . . . . . . . 91
SCI Control Register 2 (SCCR2) . . . . . . . . . . . . . . . . . . . . 92
SCI Status Register (SCSR) . . . . . . . . . . . . . . . . . . . . . . . 94
Baud Rate Register (BAUD). . . . . . . . . . . . . . . . . . . . . . . . 96
10-1
10-2
10-3
10-4
10-5
10-6
Data Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . 101
Serial Peripheral Interface Block Diagram . . . . . . . . . . . . 103
Serial Peripheral Interface
Master-Slave Interconnection. . . . . . . . . . . . . . . . . . . . . . 104
SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . 105
SPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
PI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . 109
12-1
12-2
Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Maximum Supply Current vs Internal
Clock Frequency, V_DD = 5.5 V . . . . . . . . . . . . . . . . . . . . . 136
MC68HC705C9A — Rev. 2.0
List of Figures
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