MC68HC705C9A_1 Datasheet, PDF (104/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification _{Functional Description}
The SPI is double buffered on read, but not on write. If a write is
performed during data transfer, the transfer occurs uninterrupted, and
the write will be unsuccessful. This condition will cause the write collision
(WCOL) status bit in the SPSR to be set. After a data byte is shifted, the
SPIF flag of the SPSR is set.
In the master mode, the SCK pin is an output. It idles high or low,
depending on the CPOL bit in the SPCR, until data is written to the shift
register, at which point eight clocks are generated to shift the eight bits
of data and then SCK goes idle again.
In a slave mode, the slave select start logic receives a logic low at the
SS pin and a clock at the SCK pin. Thus, the slave is synchronized with
the master. Data from the master is received serially at the MOSI line
and loads the 8-bit shift register. After the 8-bit shift register is loaded, its
data is parallel transferred to the read buffer. During a write cycle, data
is written into the shift register, then the slave waits for a clock train from
the master to shift the data out on the slave’s MISO line.
Figure 10-3 illustrates the MOSI, MISO, SCK, and SS master-slave
interconnections.
PD3/MOSI
SPI SHIFT REGISTER
76543210
SPDR ($000C)
MASTER MCU
PD2/MISO
PD5/SS
I/O PORT
PD4/SCK
SPI SHIFT REGISTER
76543210
SPDR ($000C)
SLAVE MCU
Figure 10-3. Serial Peripheral Interface Master-Slave
Interconnection
MC68HC705C9A — Rev. 2.0
Serial Peripheral Interface
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