MC68HC705C9A_1 Datasheet, PDF (140/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification _{Control Timing}
(NOTE 1)
V_DD
OSC1 PIN²
INTERNAL
CLOCK³
4064 t_CYC
INTERNAL
ADDRESS BUS³
3FFE
3FFE
3FFE
3FFE
3FFE
3FFE
3FFF
INTERNAL
DATA BUS³
NEW
NEW
PCH
PCL
RESET PIN
(NOTE 4)
NOTES:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. OSC1 line is meant to represent time only, not frequency.
3. Internal clock, internal address bus, and internal data bus are not available externally.
4. RESET outputs V_OL during 4064 POR cycles.
Figure 12-7. Power-On Reset Timing Diagram
INTERNAL
CLOCK¹
INTERNAL
ADDRESS BUS¹
INTERNAL
DATA BUS¹
RESET²
3FFE
3FFE
3FFE
3FFE
3FFF
NEW PC
NEW
NEW
OP
PCH
PCL
CODE
t_RL
NOTES:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 12-8. External Reset Timing
MC68HC705C9A — Rev. 2.0
Electrical Specifications
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