MC68HC705C9A_1 Datasheet, PDF (100/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification _Features
10.3 Features
Features include:
• Full Duplex, Four-Wire Synchronous Transfers
• Master or Slave Operation
• Bus Frequency Divided by 2 (Maximum) Master Bit Frequency
• Bus Frequency (Maximum) Slave Bit Frequency
• Four Programmable Master Bit Rates
• Programmable Clock Polarity and Phase
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Master-Master Mode Fault Protection Capability
10.4 SPI Signal Description
The four basic signals (MOSI, MISO, SCK, and SS) are described in the
following paragraphs. Each signal function is described for both the
master and slave modes.
NOTE:
In C9A mode, any SPI output line has to have its corresponding data
direction register bit set. If this bit is clear, the line is disconnected from
the SPI logic and becomes a general-purpose input line. When the SPI
is enabled, any SPI input line is forced to act as an input regardless of
what is in the corresponding data direction register bit.
MC68HC705C9A — Rev. 2.0
Serial Peripheral Interface
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