MC68HC705C9A_1 Datasheet, PDF (22/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification _{Mask Options}
1.5 Mask Options
The following two mask option registers are used to select features
controlled by mask changes on the MC68HC05C9A and the
MC68HC05C12A:
• Port B Mask Option Register (PBMOR)
• C12 Mask Option Register (C12MOR)
The mask option registers are EPROM locations which must be
programmed prior to operation of the microcontroller.
1.5.1 Port B Mask Option Register (PBMOR)
The PBMOR register, shown in Figure 1-2, contains eight
programmable bits which determine whether each port B bit (when in
input mode) has the pullup and interrupt enabled. The port B interrupts
share the vector and edge/edge-level sensitivity with the IRQ pin. For
more details, (see 4.4 External Interrupt (IRQ or Port B)).
$3FF0 Bit 7
6
5
4
3
2
1
PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1
Figure 1-2. Port B Mask Option Register
Bit 0
PBPU0
PBPU7–PBPU0 — Port B Pullup/Interrupt Enable Bits
1 = Pullup and CPU interrupt enabled
0 = Pullup and CPU interrupt disabled
NOTE: The current capability of the port B pullup devices is equivalent to the
MC68HC05C9A, which is less than the MC68HC05C12A.
MC68HC705C9A — Rev. 2.0
General Description
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