MC68HC705C9A_1 Datasheet, PDF (105/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification
SPI Registers
10.6 SPI Registers
Three registers in the SPI provide control, status, and data storage
functions. These registers are called the serial peripheral control register
(SPCR), serial peripheral status register (SPSR), and serial peripheral
data I/O register (SPDR) and are described in the following paragraphs.
10.6.1 Serial Peripheral Control Register (SPCR)
The SPI control register, shown in Figure 10-4, controls these functions:
• Enables SPI interrupts
• Enables the SPI system
• Selects between standard CMOS or open drain outputs for port D
(C9A mode only)
• Selects between master mode and slave mode
• Controls the clock/data relationship between master and slave
• Determines the idle level of the clock pin
$000A Bit 7
6
5
4
3
2
1
Read:
Write:
SPIE
SPE
DWOM
(C9A)
MSTR
CPOL
CPHA
SPR1
Reset:
0
0
0
0
0
1
U
U = Undetermined
Figure 10-4. SPI Control Register (SPCR)
Bit 0
SPR0
U
SPIE — Serial Peripheral Interrupt Enable
This read/write bit enables SPI interrupts. Reset clears the SPIE bit.
1 = SPI interrupts enabled
0 = SPI interrupts disabled
SPE — Serial Peripheral System Enable
This read/write bit enables the SPI. Reset clears the SPE bit.
1 = SPI system enabled
0 = SPI system disabled
MC68HC705C9A — Rev. 2.0
Serial Peripheral Interface
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