MC68HC705C9A_1 Datasheet, PDF (52/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification _{Power-On Reset (POR)}
CLOCK MONITOR
COP WATCHDOG
V_DD
POWER-ON RESET
STOP
RESET
INTERNAL CLOCK
R
RST
D
Q
RESET
LATCH
TO CPU AND
SUBSYSTEMS
Figure 5-1. Reset Sources
5.3 Power-On Reset (POR)
A power-on-reset occurs when a positive transition is detected on V_DD.
The power-on reset is strictly for power turn-on conditions and should
not be used to detect a drop in the power supply voltage. There is a 4064
internal processor clock cycle (t_cyc) oscillator stabilization delay after the
oscillator becomes active. (When configured as a C9A, the RESET pin
will output a logic zero during the 4064-cycle delay.) If the RESET pin is
low after the end of this 4064-cycle delay, the MCU will remain in the
reset condition until RESET is driven high externally.
5.4 RESET Pin
The function of the RESET pin is dependent on whether the device is
configured as an MC68HC05C9A or an MC68HC05C12A. When it is in
the MC68HC05C12A configuration, the pin is input only. When in
MC68HC05C9A configuration the pin is bidirectional. In both cases the
MCU is reset when a logic zero is applied to the RESET pin for a period
of one and one-half machine cycles (t_rl). For the MC68HC05C9A
configuration, the RESET pin will be driven low by a COP, clock monitor,
or power-on reset.
MC68HC705C9A — Rev. 2.0
Resets
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