MC68HC705C9A_1 Datasheet, PDF (142/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification _{Serial Peripheral Interface Timing}
Table 12-6. Serial Peripheral Interface Timing (V_DD = 3.3 Vdc)*
Num
Characteristic
Symbol
Min
Max Unit
Operating Frequency
Master
Slave
Cycle Time
1
Master
Slave
Enable Lead Time
2
Master
Slave
Enable Lag Time
3
Master
Slave
Clock (SCK) High Time
4
Master
Slave
Clock (SCK) Low Time
5
Master
Slave
Data Setup Time (Inputs)
6
Master
Slave
Data Hold Time (Inputs)
7
Master
Slave
8
Slave Access Time (Time to Data Active from
High-Impedance State)
f_OP(M)
f_OP(S)
t_CYC(M)
t_CYC(S)
t_LEAD(M)
t_LEAD(S)
t_LAG(M)
t_LAG(S)
t_W(SCKH)M
t_W(SCKH)S
t_W(SCKL)M
t_W(SCKL)S
t_SU(M)
t_SU(S)
t_H(M)
t_H(S)
t_A
dc
dc
2.0
1.0
†
500
†
1.5
720
400
720
400
200
200
200
200
0
0.5
f_OP
1.0 MHz
—
t_CYC
—
µs
—
ns
—
—
ns
—
µs
—
ns
—
—
ns
—
—
ns
—
—
ns
—
250
ns
9 Slave Disable Time (Hold Time to High-Impedance State)
t_DIS
—
500
ns
Data Valid
10 Master (Before Capture Edge)
Slave (After Enable Edge)‡
t_V(M)
t_V(S)
0.25
—
—
t_CYC(M)
500
ns
Data Hold Time (Outputs)
11 Master (After Capture Edge)
Slave (After Enable Edge)
t_HO(M)
t_HO(S)
0.25
0
—
t_CYC(M)
—
ns
Rise Time (20% V_DD to 70% V_DD, C_L = 200 pF)
12 SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
t_RM
—
200
ns
t_RS
—
2.0
µs
Fall Time (70% V_DD to 20% V_DD, C_L = 200 pF)
13 SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
t_FM
—
200
ns
t_FS
—
2.0
µs
NOTES:
* V_DD = 3.3 Vdc ± 0.3 Vdc; V_SS = 0 Vdc, T_A = –40 to +85 °C. Refer to Figure 12-7 and Figure 12-8 for timing diagrams.
† Signal production depends on software
‡ Assumes 200 pF load on all SPI pins.
MC68HC705C9A — Rev. 2.0
Electrical Specifications
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