MC68HC705C9A_1 Datasheet, PDF (46/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification _Introduction
NOTE: The current instruction is the one already fetched and being operated on.
When the current instruction is complete, the processor checks all
pending hardware interrupts. If interrupts are not masked (CCR I bit
clear) and if the corresponding interrupt enable bit is set, the processor
proceeds with interrupt processing; otherwise, the next instruction is
fetched and executed.
If an external interrupt and a timer, SCI, or SPI interrupt are pending at
the end of an instruction execution, the external interrupt is serviced first.
The SWI is executed the same as any other instruction, regardless of the
I-bit state.
Table 4-1 shows the relative priority of all the possible interrupt sources.
Figure 4-1 shows the interrupt processing flow.
Function
Reset
Software
Interrupt
(SWI)
External
Interrupt
Timer
Interrupts
SCI
Interrupts
SPI
Interrupts
Table 4-1. Vector Addresses for Interrupts and Resets
Source
Power-On-Reset
RESET Pin
COP Watchdog
Local
Mask
None
Global
Mask
None
Priority
(1 = Highest)
1
User Code
None
None
Same Priority
As Instruction
IRQ Pin
Port B Pins
None
I Bit
2
ICF Bit
ICIE Bit
OCF Bit
OCIE Bit
I Bit
3
TOF Bit
TOIE Bit
TDRE Bit
TC Bit
TCIE Bit
RDRF Bit
I Bit
4
RIE Bit
OR BIt
IDLE Bit
ILIE Bit
SPIF Bit
SPIE
I Bit
5
MODF Bit
Vector
Address
$3FFE–$3FFF
$3FFC–$3FFD
$3FFA–$3FFB
$3FF8–$3FF9
$3FF6–$3FF7
$3FF4–$3FF5
MC68HC705C9A — Rev. 2.0
Interrupts
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