MC68HC705C9A_1 Datasheet, PDF (53/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification
RESET Pin
VDD
tVDDR
OSC12
INTERNAL
CLOCK1
INTERNAL
ADDRESS
BUS1
INTERNAL
DATA
BUS1
RESET
(C9A)
4064tCYC
tCYC
3FFE 3FFF
NEW NEW
PC
PC
NEW
PCH
NEW _DUMMY OP
PCL
CODE
4
3FFE
3FFE
3FFE
3FFE
3FFF
NEW
PC
NEW
PC
tRL
3
PCH
PCL
DUMMY ^OP
CODe
RESET
(C12A)
tRL
3
NOTES:
1. Internal timing signal and bus information are not available externally.
2. OSC1 line is not meant to represent frequency. It is only meant to represent time.
3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence.
4. RESET outputs V_OL during 4064 power-on reset cycles when in C9A mode only.
Figure 5-2. Power-On Reset and RESET
MC68HC705C9A — Rev. 2.0
Resets
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