MC68HC705C9A_1 Datasheet, PDF (63/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification — MC68HC705C9A
Section 7. Input/Output Ports
7.1 Contents
7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
7.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
7.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
7.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
7.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
7.2 Introduction
This section briefly describes the 31 I/O lines arranged as one 7-bit and
three 8-bit ports. All of these port pins are programmable as either inputs
or outputs under software control of the data direction registers.
NOTE: To avoid a glitch on the output pins, write data to the I/O port data
register before writing a one to the corresponding data direction register.
7.3 Port A
Port A is an 8-bit bidirectional port which does not share any of its pins
with other subsystems. The port A data register is at $0000 and the data
direction register (DDR) is at $0004. The contents of the port A data
register are indeterminate at initial powerup and must be initialized by
user software. Reset does not affect the data registers, but clears the
data direction registers, thereby returning the ports to inputs. Writing a
one to a DDR bit sets the corresponding port bit to output mode. A block
diagram of the port logic is shown in Figure 7-1.
MC68HC705C9A — Rev. 2.0
Input/Output Ports
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