MC68HC705C9A_1 Datasheet, PDF (137/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification
Control Timing
12.7 Control Timing
Table 12-3. Control Timing (V_DD = 5.0 V ±10%)⁽¹⁾
Characteristic
Symbol
Min
Max
Unit
Frequency of Operation
Crystal
External Clock
f_OSC
—
DC
4.2
MHz
4.2
Internal Operating Frequency (f_OSC ÷ 2)
Crystal
External Clock
f_OP
—
DC
2.1
MHz
2.1
Cycle Time
Crystal Oscillator Startup Time
Stop Recovery Start-up Time (Crystal Oscillator)
RESET Pulse Width
Timer
Resolution⁽²⁾
Input Capture Pulse Width
Input Capture Pulse Period
t_CYC
480
t_OXOV
—
t_ILCH
—
t_RL
1.5
t_RESL
4.0
t_TH, t_TL
125
t_TLTL
(3)
—
ns
100
ms
100
ms
—
t_CYC
—
t_CYC
—
ns
—
t_CYC
Interrupt Pulse Width Low (Edge-Triggered)
t_ILIH
125
—
ns
Interrupt Pulse Period
t_ILIL
(4)
—
t_CYC
OSC1 Pulse Width
t_OH,t_OL
90
—
ns
NOTES:
1. V_DD = 5.0 Vdc ± 10%, V_SS = 0 Vdc, T_A = –40 to +85 °C, unless otherwise noted
2. Because a 2-bit prescaler in the timer must count four internal cycles (t_CYC), this is the limiting
minimum factor in determining the timer resolution.
3. The minimum period t_TLTL should not be less than the number of cycle times it takes to execute the
capture interrupt service routine plus 24 t_CYC.
4. The minimum t_ILIL should not be less than the number of cycle times it takes to execute the
interrupt service routine plus 19 t_CYC.
MC68HC705C9A — Rev. 2.0
Electrical Specifications
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