MC68HC705C9A_1 Datasheet, PDF (143/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification
Serial Peripheral Interface Timing
SS
(INPUT)
SS pin of master held high.
1
SCK (CPOL = 0)
(OUTPUT)
NOTE
4
SCK (CPOL = 1)
(OUTPUT)
NOTE
5
MISO
(INPUT)
10 (ref)
MOSI
(OUTPUT)
13
MSB IN
11
MASTER MSB OUT
12
5
12
4
BIT 6–1
10
BIT 6–1
13
12
13
6
7
LSB IN
11 (ref)
MASTER LSB OUT
12
NOTE:
This first clock edge is generated internally, but is not seen at the SCK pin.
a) SPI Master Timing (CPHA = 0)
SS
(INPUT)
SCK (CPOL = 0)
(OUTPUT)
SS pin of master held high.
1
5
4
SCK (CPOL = 1)
(OUTPUT)
5
4
MISO
(INPUT)
10 (ref)
MOSI
(OUTPUT)
13
MSB IN
11
MASTER MSB OUT
13
12
12
13
BIT 6–1
10
BIT 6–1
6
7
LSB IN
11
MASTER LSB OUT
12
NOTE:
This last clock edge is generated internally, but is not seen at the SCK pin.
b) SPI Master Timing (CPHA = 1)
NOTE
NOTE
Figure 12-9. SPI Master Timing Diagram
MC68HC705C9A — Rev. 2.0
Electrical Specifications
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