MC68HC705C9A_1 Datasheet, PDF (76/157 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
General Release Specification _{Timer I/O Registers}
8.4.6 Output Compare Registers (OCRH and OCRL)
When the value of the 16-bit counter matches the value in the output
compare registers, the planned TCMP pin action takes place. Writing to
OCRH before writing to OCRL inhibits timer compares until OCRL is
written. Reading or writing to OCRL after the timer status register clears
the output compare flag (OCF).
OCRH
$0016
Write:
Read:
Bit 7
BIT15
6
BIT14
5
4
3
2
BIT13 BIT12 BIT11 BIT10
Unaffected by Reset
1
BIT9
Bit 0
BIT8
OCRL
$0017
Write:
Read:
Bit 7
BIT7
6
BIT6
5
4
3
2
BIT5
BIT4
BIT3
BIT2
Unaffected by Reset
1
BIT1
Bit 0
BIT0
Figure 8-7. Output Compare Registers (OCRH and OCRL)
To prevent OCF from being set between the time it is read and the time
the output compare registers are updated, use this procedure:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to OCRH. Compares are now inhibited until OCRL is written.
3. Clear bit OCF by reading timer status register (TSR).
4. Enable the output compare function by writing to OCRL.
5. Enable interrupts by clearing the I bit in the condition code
register.
MC68HC705C9A — Rev. 2.0
Capture/Compare Timer
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