Z80182 Datasheet, PDF (98/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
General-Purpose I/O Port Timing
This figure shows the timing for the Ports A, B and C.
Parameters referred to in this figure appear in Tables D
and E.
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
I/O Port Timing (Output)
T1
T2
TW
T3
T1
T2
TW
T3
T1
T2
TW
T3
0
A0-A7
/IORQ
Port Data Dir. Reg. Addr. (Input)
F1
F4
Port Data Reg. Addr. (Input)
F1
F4
Port Data Reg. Addr. (Input)
F1
F4
D0-D7
/WR
Port
(In) 'OO'H (Change Port To Output)
F8
F2
F9
F2
E3
Port (Output)
Port Output Data 1 (In)
F8
E3
F9
F2
Port Output Data 1 (Out)
Port Output Data 2 (In)
F8
E3
Port Output Data 2 (Out)
I/O Port Timing (Input)
A0-A7
Port Data Dir. Reg. Addr. (Input)
/IORQ
D0-D7
F4
(In) 'FF'H (Change Port To Input)
/WR
/RD
E4
Previous Output
Port
Port Data Reg. Addr. (Input)
F5
Port Data 1 (Out)
Port Data Reg.
F5
Port Data 2 Out
F3
F6
E1
E2
Port Input Data 1 (In)
F3
F6
E2
E1
Port Input Data 2 (In)
Figure 107. PORT Timing
3-98
DS971820600