Z80182 Datasheet, PDF (25/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
On the MPU interface, the transmitted data available can
be programmed to interrupt the MPU on 1, 4, 8 or 14 bytes
of available data by seeing the appropriate value in the
MPU FSCR control register (MPU write only xxECH) bits 6
and 7. A timeout feature exists, Transmit Timeout Timer,
which is an additional 8-bit timer with SCC TxRCB as the
input source. If the transmitter FIFO is non-empty and no
PC write or MPU read of the FIFO has taken place within the
timer interval, a timeout occurs causing a corresponding
interrupt to the MPU.
Z80182/Z8L182 MIMIC SYNCHRONIZATION CONSIDERATIONS
Because of the asynchronous nature of the FIFO’s on the
MIMIC, some synchronization plan must be provided to
prevent conflict from the dual port accesses of the MPU
and the PC.
To solve this problem, I/O to the FIFO is buffered and the
buffers allow both PC and MPU to access the FIFO
asynchronously. Read and Write requests are then
synchronized by means of the MPU clock. Incoming signals
are buffered in such a way that metastable input levels are
stabilized to valid 1 or 0 levels. Actual transfers to and from
the buffers, from and to the FIFO memory, are timed by the
MPU clock. ALU evaluation is performed on a different
phase than the transfer to ensure stable pointer values.
Another potential problem is that of simultaneous access
of the MPU and PC to any of the various ‘mailbox’ type
registers. This is solved by dual buffering of the various
read/write registers. During a read access by either the
MPU or PC to a mailbox register, the data in the output or
slave portion of the buffered register is not permitted to
change. Any write that might take place during this time
will be stored in the input of master part of the register. The
corresponding status/interrupt is reset appropriately based
on the write having followed the read to the register. For
example, the IUS/IP bit for the LCR write will not be cleared
by the MPU read of the LCR if a simultaneous write to the
LCR by the PC takes place. Instead the LSR data will
change after the read access and IUS/IP bit 3 remains at
logic 1.
DS971820600
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