Z80182 Datasheet, PDF (39/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
DMA REGISTERS
DAR0L
Read/Write
DA7
Addr 23H
DA0
PRELIMINARY
MAR1L
Read/Write
MA7
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
Addr 28H
MA0
DAR0H
Read/Write
DA15
Addr 24H
DA8
DAR0B
Read/Write
Addr 25H
DA19 DA16
- ---
Bits 0-2 (3) are used for DAR0B
A19, A18, A17, A16 DMA Transfer Request
x x 0 0 /DREQ0 (external)
x x 0 1 TDR0 (ASCI0)
x x 1 0 TDR1 (ASCI1)
x x 1 1 Not Used
Figure 35. DMA 0 Destination Address Registers
BCR0L
Read/Write
BC7
Addr 26H
BC0
BCR0H
Read/Write
BC15
Addr 27H
BC8
Figure 36. DMA 0 Byte Counter Registers
MAR1H
Read/Write
MA15
Addr 29H
MA8
MAR1B
Read/Write
Addr 2AH
MA19 MA16
----
Figure 37. DMA 1 Memory Address Registers
IAR1L
Read/Write
IA7
Addr 2BH
IA0
IAR1H
Read/Write
IA15
Addr 2CH
IA8
Figure 38. DMA I/O Address Registers
BCR1L
Read/Write
BC7
Addr 2EH
BC0
BCR1H
Read/Write
BC15
Addr 2FH
BC8
Figure 39. DMA 1 Byte Count Registers
DS971820600
3-39