Z80182 Datasheet, PDF (84/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
TIMING DIAGRAMS (Continued)
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
Ø
32
31
/INTI
33
/NMI
C7
/INTSCC [4]
/M1 [1]
29
/IORQ [1]
/Data IN [1]
39
/MREQ [2]
41
40
/RFSH [2]
35
34
35
34
/BUSREQ
36
37
/BUSACK
Address
Data /MREQ,
/RD, /WR,
/IORQ
38
43
[3]
/HALT
Notes:
[1] During /INT0 acknowledge cycle [3] Output buffer is off at this point
[2] During refresh cycle
[4] Refer to Table C, parameter 7
16
15
43
38
44
Figure 91. CPU Timing
(/INT0 Acknowledge Cycle, Refresh Cycle, BUS RELEASE Mode
HALT Mode, SLEEP Mode, SYSTEM STOP Mode)
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DS971820600