Z80182 Datasheet, PDF (47/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
When the part is in IDLE mode, the clock oscillator is kept
oscillating, but the clock to the rest of the internal circuit,
including the CLKOUT, is stopped completely. IDLE mode
is exited in a similar way as STANDBY mode, i.e., RESET,
BUS REQUEST or EXTERNAL INTERRUPTS, except that
the 2¹⁷ bit wake-up timer is bypassed; all control signals are
asserted eight clock cycles after the exit conditions are
gathered.
STANDBY-QUICK RECOVERY Mode
STANDBY-QUICK RECOVERY mode is an option offered
in STANDBY mode to reduce the clock recovery time in
STANDBY mode from 2¹⁷ clock cycles (6.5 ms at 20 MHz)
to 2⁶ clock cycles (3.2 µs at 20 MHz). This feature can only
be used when providing an oscillator as clock source.
To enter STANDBY-QUICK RECOVERY mode:
1. Set D6 and D3 to 1 and 1, respectively.
2. Set the I/O STOP bit (D5 of ICR,
I/O Address = 3FH) to 1.
When the part is in STANDBY-QUICK RECOVERY mode,
the operation is identical to STANDBY mode except when
exit conditions are gathered, i.e., RESET, BUS REQUEST
or EXTERNAL INTERRUPTS; the clock and other control
signals are recovered sooner than the STANDBY mode.
Note: If STANDBY-QUICK RECOVERY is enabled, the
user must make sure stable oscillation is obtained within
64 clock cycles.
CPU Control Register
The Z8S180 has an additional register which allows the
programmer to select options that directly affect the CPU
performance as well as controlling the STANDBY operating
mode of the chip. The CPU Control Register (CCR) allows
the programmer to change the divide-by-two internal clock
to divide-by-one. In addition, applications where EMI noise
is a problem, the Z8S180 can reduce the output drivers on
selected groups of pins to 25% of normal pad driver
capability which minimizes the EMI noise generated by the
part.
3. Execute the SLEEP instruction.
CPU Control Register (CCR) Addr 1FH
D7 D6 D5 D4 D3 D2 D1 D0
00000000
Clock Divide
0 = XTAL/2
1 = XTAL/1
Standby/Idle Enable
00 = No Standby
01 = Idle After Sleep
10 = Standby After Sleep
11 = Standby After Sleep
64 Cycle Exit
(Quick Recovery)
BREXT
0 = Ignore BUSREQ
In Standby/Idle
1 = Standby/Idle Exit
on BUSREQ
LNAD/DATA
0 = Standard Drive
1 = 25% Drive On
A19-A0, D7-D0
LNCPUCTL
0 = Standard Drive
1 = 25% Drive On CPU
Control Signals
Reserved
LNPHI
0 = Standard Drive
1 = 25% Drive On
EXT.PHI Clock
Figure 51. CPU Control Register
DS971820600
3-47