Z80182 Datasheet, PDF (12/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
Ports B and C Multiplexed Pin Descriptions
Ports B and C are pin multiplexed with the Z180 ASCI
functions and part of ESCC channel A. The MUX function
is controlled by bits 7-5 in the System Configuration Register.
The MUX is organized as shown in Table 4.
Note 1:
When the Port function (PB1) is selected, the internal Z180/
CTS0 is always driven Low. This ensures that the ASCI
channel 0 of the Z180^™ MPU is enabled to transmit data.
Table 4. Multiplexed Port Pins
Port Mode
Function
ASCI/ESCC Mode
Function
PB7
PB6 Select with bit 6=1
PB5 System Config Reg.
PB4
PB3
PB2 Select with bit 5=1
PB1 System Config Reg.
PB0
PC7
PC6
PC5
PC4
PC3 Select with bit 7=1
PC2 System Config Reg.
PC1
PC0
RxS,/CTS1
RxA1
TxA1
RxA0
TxA0
/DCD0
/CTS0 (Note 1)
/RTS0
Always Reads /INT2 Ext.
Status
Always Reads /INT1 Ext.
Status
/W//REQA
/SYNCA
/DTR//REQA
/RTSA (Note 2)
/CTSA
/DCDA
Note 2:
Interrupt Edge /Pin MUX register, bit 3 chooses between
the /MWR or PC2//RTSA combination; the System
Configuration Register bit 7 chooses between PC2 and
/RTSA.
Refer to Table 5 for the 1st, 2nd and 3rd pin functions.
3-12
DS971820600