Z80182 Datasheet, PDF (19/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
The following features are common to both the ESCC and s NRZ, NRZI or FM encoding/decoding. Manchester
the CMOS SCC:
Code Decoding (Encoding with External Logic).
s Two independent full-duplex channels
s Baud Rate Generator in each Channel
s Synchronous/Isochronous data rates:
- Up to 1/4 of the PCLK using external clock source
- Up to 5 Mbits/sec at 20 MHz PCLK (ESCC).
s Digital Phase-Locked Loop (DPLL) for Clock Recovery
s Crystal Oscillator
s Asynchronous capabilities
- 5, 6, 7 or 8 bits/character (capable of handling
4 bits/character or less)
- 1, 1.5, or 2 stop bits
- Odd or even parity
- Times 1, 16, 32 or 64 clock modes
- Break generation and detection
- Parity, overrun and framing error detection
s Byte oriented synchronous capabilities:
- Internal or external character synchronization
- One or two sync characters (6 or 8 bits/sync
character) in separate registers
- Automatic Cyclic Redundancy Check (CRC)
generation/detection
The following features are implemented in the ESCC^™ for
the Z80182/Z8L182 only:
s New 32-bit CRC-32 (Ethernet Polynomial)
s ESCC Programmable Clock
- programmed to be equal to system clock
divided by one or two
- programmed by Z80182 Enhancement Register
Note: The ESCC^™ programmable clock must be
programmed to divide-by-two mode when operating above
the following conditions:
– PHI > 20 MHz at 5.0V
s SDLC/HDLC capabilities:
- Abort sequence generation and checking
- Automatic zero insertion and detection
- Automatic flag insertion between messages
- Address field recognition
- I-field residue handling
- CRC generation/detection
- SDLC loop mode with EOP recognition/loop entry
and exit
– PHI > 10 MHz at 3.0V
DS971820600
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