Z80182 Datasheet, PDF (45/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
ADDITIONAL FEATURES ON THE Z182 MPU
The following is a detailed description of the enhancements
to the Z8S180 from the standard Z80180 in the areas of
STANDBY, IDLE, and STANDBY-QUICK RECOVERY
modes.
Add-On Features
There are five different power-down modes. SLEEP and
SYSTEM STOP are inherited from the Z80180. In SLEEP
mode, the CPU is in a stopped state while the on-chip
I/Os are still operating. In I/O STOP mode, the on-chip I/Os
are in a stopped state while leaving the CPU running. In
SYSTEM STOP mode, both the CPU and the on-chip I/Os
are in the stopped state to reduce the current consumption.
The Z8S180 has added two additional power-down modes,
STANDBY and IDLE, to reduce the current consumption
even further. The differences among these power-down
modes are summarized in Table 10.
Power-Down
Modes
SLEEP
I/O STOP
SYSTEM STOP
IDLE^†
STANDBY^†
CPU
Core
Stop
Running
Stop
Stop
Stop
On-Chip
I/O
Running
Stop
Stop
Stop
Stop
Table 10. Power Down Modes
OSC.
Running
Running
Running
Running
Stop
CLKOUT
Running
Running
Running
Stop
Stop
Recovery
Source
RESET, Interrupts
By Programming
RESET, Interrupts
RESET, Interrupts, BUSREQ
RESET, Interrupts, BUSREQ
Notes:
† _{IDLE and STANDBY modes are only offered in Z8S180. Note that the}
minimum recovery time can be achieved if INTERRUPT is used as the
Recovery Source.
Recovery Time
(Minimum)
1.5 Clock
-
1.5 Clock
8 +1.5 Clock
2¹⁷ +1.5 Clock (Normal Recovery)
2⁶ +1.5 Clock (Quick Recovery)
STANDBY Mode
The Z8S180 has been designed to save power. Two low-
power programmable power-down modes have been
added; STANDBY mode and IDLE mode. The
STANDBY/IDLE mode is selected by multiplexing D6 and
D3 of the CPU Control Register (CCR, I/O Address = 1FH).
To enter STANDBY mode:
1. Set D6 and D3 to 1 and 0, respectively.
2. Set the I/O STOP bit (D5 of ICR,
I/O Address = 3FH) to 1.
3. Execute the SLEEP instruction.
When the part is in STANDBY mode, it behaves similar to
the SYSTEM STOP mode which currently exists on the
Z80180, except that the STANDBY mode stops the external
oscillator, internal clocks and reduces power consumption
to typically 50 µA..
Since the clock oscillator has been stopped, a restart of
the oscillator requires a period of time for stabilization. An
18-bit counter has been added in the Z8S180 to allow for
oscillator stabilization. When the part receives an external
IRQ or BUSREQ during STANDBY mode, the oscillator is
restarted and the timer counts down 2¹⁷ counts before
acknowledgment is sent to the interrupt source.
The recovery source needs to remain asserted for duration
of the 2¹⁷ count, otherwise standby will be resumed.
The following is a description of how the part exits STANDBY
for different interrupts and modes of operation.
STANDBY Mode Exit with /RESET
The /RESET input needs to be asserted for a duration long
enough for the crystal oscillator to stabilize and then exit
from the STANDBY mode. When /RESET is de-asserted, it
goes through the normal reset timing to start instruction
execution at address (logical and physical) 0000H.
The clocking is resumed within the Z8S180 and at the
system clock output after /RESET is asserted when the
crystal oscillator is restarted, but not yet stabilized.
DS971820600
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