Z80182 Datasheet, PDF (85/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
T1
0
Address
/IROQ
/RD
/WR
PRELIMINARY
I/O Read Cycle
T2
TW
T3
I/O Write Cycle
T1
T2
TW
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
T3
28
29
28
29
9
13
22
25
Figure 92. CPU Timing
Ø
/DREQi
(At level
sense)
/DREQi
(At edge
sence)
/TENDi
ST
CPU or DMA Read/Write Cycle (Only DMA Write Cycle for /TENDi)
T1
T2
Tw
T3
T1
45
46 ^[1]
45
45 ^[2]
47
[3]
17
18
[4]
48
DMA Control Signals
[1] tDRQS and tDRQH are specified for the rising edge of clock followed by T3.
[2] tDRQS and tDRQH are specified for the rising edge of clock.
[3] DMA cycle starts.
[4] CPU cycle starts.
Figure 93. DMA Control Signals
DS971820600
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