Z80182 Datasheet, PDF (71/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
Although this bit is disabled by default, it is advised that
this bit is enabled to prevent interrupt conflict between
MIMIC and ESCC interrupts.
Bits 3-1 Interrupt ID Bits
This 3-bit field is used to determine the highest priority
interrupt pending (see Table 19).
D7 D6 D5 D4 D3 D2 D1 D0
0 0 000000
0 if Interrupt Pending
Interrupt ID bit (0)
Interrupt ID bit (1)
Interrupt ID bit (2)
Always '0'
Always '0'
FIFO Enabled Flag
FIFO Enabled Flag
Figure 73. Interrupt Identification Register
(PC Read Only, Address 02H)
(Z180 MPU no access)
Interrupt Identification Register
Bit 0 Interrupt Pending
This bit is logic 0 and interrupt is pending.
When the PC accesses the IIR, the contents of the register
and all pending interrupts are frozen. Any new interrupts
will be recorded, but not acknowledged, during the IIR
access.
D7 D6 D5 D4 D3 D2 D1 D0
0 0 000000
Data Ready
Overrun Error
Parity Error
Framing Error
Break Interrupt
THRE
TEMT
Error in RCVR FIFO
Bit 7 and Bit 6 FIFO’s Enabled
These bits will read 1 if the FIFO mode is enabled on the
MIMIC.
Bit 5 and Bit 4 Always Read 0
Reserved bits.
Figure 74. Line Status Register
(PC Read Only, Address 05H)
(Z180 MPU Read/Write bits 6, 4, 3, 2, Address xxF5H)
b3 b2 b1 Priority
0
1
1 Highest
0
1
0
2nd
1
1
0
2nd
0
0
1
3rd
0
0
0
4th
Table 19. Interrupt Identification Field
Interrupt Source
INT Reset Control
Overrun, Parity, Framing error
or Break detect bits set by MPU
Read Line Status Register
Received Data trigger level
RCVR FIFO drops below trigger level
Receiver Timeout with data
in RCVR FIFO.
Read RCVR FIFO
Transmitter Holding
Register Empty.
Writing to the Transmitter Holding
Register or reading the Interrupt
Identification Register when the
THRE is the source of the interrupt.
MODEM status: CTS,
DSR, RI or DCD
Reading the MODEM
status register.
DS971820600
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