Z80182 Datasheet, PDF (58/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
Z182 MISCELLANEOUS CONTROL AND INTERFACE REGISTERS
Table 12b. Data Bus Direction (Z182 Bus Master)
Interrupt Acknowledge Transaction
Intack For
On-Chip
Peripheral (IEI=1)
Intack For
Off-Chip
Peripheral (IEI=0)
Z80182/Z8L182
Data Bus
Z
In
(DD =0)
OUT
Z80182/Z8L182
Data Bus
Out
In
(DD_OUT=1)
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
Table 13a. Data Bus Direction (Z80182/Z8L182 is not Bus Master)
I/O And Memory Transactions
I/O Write
I/O Read
I/O Write
I/O Read
Write Read
to On-Chip From On-Chip to Off-Chip From Off-Chip To
From
Peripherals Peripherals Peripherals Peripherals Memory Mode
Refresh
Z80182
Idle Mode
Z80182
In
Out
Z
/Z8L182
Data Bus
DD =0)
OUT
Z80182
In
Out
Z
/Z8L182
Data Bus
(DD_OUT=1)
Z
Z
In
Z
Z
Z
Z
In
Z
Z
Table 13b. Data Bus Direction (Z80182/Z8L182 is not Bus Master)
Interrupt Acknowledge Transaction
Intack For
On-Chip
Peripheral
Intack For
Off-Chip
Peripheral
Z80182/Z8L182
Data Bus
Out
In
(DD =0)
OUT
Z80182/Z8L182
Data Bus
Out
In
(DD_OUT=1)
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DS971820600