Z80182 Datasheet, PDF (33/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
STAT0
Bit RDRF OVRN PE
Upon Reset
0
0
0
R/W
R
R
R
Addr 04H
FE RIE /DCD0 TDRE TIE
0
0
† †† 0
R R/W R
R R/W
Transmit Interrupt Enable
Transmit Data Register
Empty
Data Carrier Detect
Receive Interrupt Enable
Framing Error
Parity Error
Over Run Error
Receive Data Register Full
† /DCD0 - Depending on the condition of /DCD0 Pin.
†† /CTS0 Pin TDRE
L
1
H
0
Figure 13. ASCI Status Register
STAT1
Addr 05H
Bit RDRF OVRN PE FE RIE CTS1E TDRE TIE
Upon Reset
0
0
0
00
0
1
0
R/W
R
R
R
R R/W R/W R R/W
Transmit Interrupt Enable
Transmit Data Register
Empty
/CTS1 Enable
Receive Interrupt Enable
Framing Error
Parity Error
Over Run Error
Receive Data Register Full
Figure 14. ASCI Status Register (Ch. 1)
DS971820600
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