Z80182 Datasheet, PDF (86/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
TIMING DIAGRAMS (Continued)
PRELIMINARY
T1
T2
Tw
Tw
Ø
49
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
T3
50
49
50
49
50
D7-D0
15
16
Figure 94. E Clock Timing
(Memory Read/Write Cycle
I/O Read/Write Cycle)
Ø
BUS RELEASE Mode
E SLEEP Mode
SYSTEM STOP Mode
49
50
Figure 95. E Clock Timing
3-86
DS971820600