Z80182 Datasheet, PDF (55/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
Read Register 0
D7 D6 D5 D4 D3 D2 D1 D0
PRELIMINARY
Read Register 3
D7 D6 D5 D4 D3 D2 D1 D0
Rx Character Available
Zero Count
Tx Buffer Empty
DCD
Sync/Hunt
CTS
Tx Underrun/EOM
Break/Abort
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
0
0
0
Ext/Status IP
Tx IP
Rx IP
0
0
Read Register 1
D7 D6 D5 D4 D3 D2 D1 D0
All Sent
Residue Code 2
Residue Code 1
Residue Code 0
Parity Error
Rx Overrun Error
CRC/Framing Error
End of Frame (SDLC)
Read Register 2
D7 D6 D5 D4 D3 D2 D1 D0
V0
V1
V2
V3
Interrupt
Vector
V4
V5
V6
V7
Read Register 6*
D7 D6 D5 D4 D3 D2 D1 D0
BC0
BC1
BC2
BC3
BC4
BC5
BC6
BC7
*Can only be accessed if the SDLC FIFO enhancement
is enabled (WR15 bit D2 set to 1)
SDLC FIFO Status and Byte Count (LSB)
Read Register 7*
D7 D6 D5 D4 D3 D2 D1 D0
BC8
BC9
BC10
BC11
BC12
BC13
FDA: FIFO Data Available
1 = Status Reads from FIFO
0 = Status Reads from EMSCC
FOS: FIFO Overflow Status
1 = FIFO Overflowed
0 = Normal
*Can only be accessed if the SDLC FIFO enhancement
is enabled (WR15 bit D2 set to 1)
SDLC FIFO Status and Byte Count (LSB)
Figure 52. Write Register Bit Functions (Continued)
DS971820600
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