Z80182 Datasheet, PDF (95/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
Table C. Z85230 General Timing Table
No.
Symbol
Parameter
20 MHz
Min
Max
1
TdPC(REQ)
2
TdPC(W)
3
TsRxC(PC)
4
TsRxD(RxCr)
/PCLK to W/REQ Valid
/PCLK to Wait Inactive
/RxC to /PCLK Setup Time
RxD to /RxC Setup Time
70
170
N/A
0
5
ThRxD(RxCr)
6
TsRxD(RxCf)
7
ThRxD(RxCf)
8
TsSY(RxC)
RxD to /RxC Hold Time
45
RxD to /RxC Setup Time
0
RxD to /RxC Hold Time
45
/SYNC to /RxC Setup Time
–90
9
ThSY(RXC)
10
TsTxC(PC)
11
TdTxCf(TXD)
12
TdTxCr(TXD)
/SYNC to/RxC Hold Time
/TxC to /PCLK Setup Time
/TxC to TxD Delay
/TxC to TxD Delay
5TcPc
N/A
70
70
13
TdTxD(TRX)
14
TwRTxh
15
TwRTxI
16a
TcRTx
TxD to TRxC Delay
RTxC High Width
TRxC Low Width
RTxC Cycle Time
70
70
70
200
16b
TxRx(DPLL)
17
TcRTxx
18
TwTRxh
19
TwTRxl
DPLL Cycle Time Min
Crystal Osc. Period
TRxC High Width
TRxC Low Width
50
61
1000
70
70
20
TcTRx
21
TwExT
22
TwSY
TRxC Cycle Time
DCD or CTS Pulse Width
SYNC Pulse Width
Notes:
These AC parameter values are preliminary and subject to change without notice.
[1] RxC is /RTxC or /TRxC, whichever is supplying the receive clock.
[2] TxC is /TRxC or /RTxC, whichever is supplying the transmit clock.
[3] Both /RTxC and /SYNC have 30 pF capacitors to ground connected to them.
[4] Synchronization of RxC to PCLK is eliminated in divide by four operation.
[5] Parameter applies only to FM encoding/decoding.
[6] Parameter applies only for transmitter and receiver; DPLL and baud
rate generator timing requirements are identical to case PCLK requirements.
[7] The maximum receive or transmit data rate is 1/4 PCLK.
[8] Applies to DPLL clock source only. Maximum data rate of 1/4 PCLK
still applies. DPLL clock should have a 50% duty cycle.
200
60
60
Notes
[1,4]
[1]
[1]
[1,5]
[1,5]
[1]
[1]
[2,4]
[2]
[2,5]
[6]
[6]
[6,7]
[7,8]
[3]
[6]
[6]
[6,7]
DS971820600
3-95