Z80182 Datasheet, PDF(2/109 Page) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

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Z80182 Datasheet, PDF (2/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

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Zilog

PRELIMINARY

GENERAL DESCRIPTION (Continued)

D7-D0

Control

GLU

A19-A0

Logic

Bus

Transceiver

Tx Data

Rx Data

ESCC

Control

85230

ESCC

Channel

Z8S180

(Static Z80180)

MPU Core

/TRxCB

85230

ESCC

Channel

Z80182/Z8L182

ZILOG INTELLIGENT PERIPHERAL

EV1

EV2

/ROMCS

/RAMCS

Address

Decode

16550

MIMIC

Interface

8-Bit Parallel

Port C

8-Bit Parallel

Port B

8-Bit Parallel

Port A

85230

ESCC Ch. A

or Port C

Z180 Signals

or Port B

MUX

16550 MIMIC

or ESCC

85230 Ch. B

and Port A

Note: Conventional use of the term "MPU side" refers to all interface through the Z180 MPU

core and "PC side" refers to all interface through the16550 MIMIC interface.

Figure 1. Z80182/Z8L182 Functional Block Diagram

3-2

DS971820600

▷