Z80182 Datasheet, PDF (105/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
No. Sym
16
tHR
17
TSTI
18
TIR
/HRD
RD_RBR
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
Table L. Interrupt Timing Transmitter FIFO
Parameter
Z8L182
20 MHz
Min
Max
Delay from /WR
(WR THR) to Reset
Interrupt
2.5 MPU
Clock Cycles
Delay from Stop to
Interrupt (THRE)
2 MPU
Clock Cycles
Delay from /RD
75
(RD IIR) to Reset
Interrupt (THRIE)
Z80182
33 MHz
Min
Max
2.5 MPU
Clock Cycles
2 MPU
Clock Cycles
75
/WR (MPU) RCVR
FIFO (First Byte
that reaches
Trigger Level)
/HRXRDY
/HWR
(Host)
THR
RD (MPU)
THR (Last
Byte Model)
/HTxRDY
Note: If FCR0-1
TSINT=3 CPU
Clock Cycles
DS971820600
19
14
20
21
Figure 116 RCVR FIFO Bytes Other Than First
3-105