Z80182 Datasheet, PDF (57/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
Z182 MISCELLANEOUS CONTROL AND INTERFACE REGISTERS
Figures 54 through 65 describe miscellaneous registers
that control the Z182 configuration, RAM/ROM chip select,
interrupt and various status and timers.
D7 D6 D5 D4 D3 D2 D1 D0
0000000 0
System Configuration Register
Bit 7 Port C Select
When this bit is set to 1, bit 8 parallel Port C is selected on
the multiplexed pins. When this bit is reset to 0 then these
multiplexed pins take ESCC^™ Channel A functions.
Daisy Chain
0=ESCC > 16550 MIMIC
1=16550 MIMIC> ESCC
ESCC/MIMIC
0=ESCC Channel B
1=16550 MIMIC Interface
Tri-Muxed Pins
0=Z80180
1=ESCC Channel/16550 MIMIC
Disable ROMs
0=ROM Sel Enabled
1=ROM Sel Disabled
DOUT
0=No Data Out
1=Data Out
Port PB4-PB0 Select
0=ASCI Channel 0 Func
1=PB4-PB0 Selected
Port PB7-PB5 Select
0=RXA1, TXA1, (RXS,/CTS1)
1=PB7-PB5 Selected
Port C Select
0=ESCC Channel A Func
1=Port C Selected
Figure 54. System Configuration Register
(Z180 MPU Read/Write, Address xxEFH)
Bit 6 PB7-PB5 Select
When this bit is set to 1, parallel Port B bits 7 through 5 are
selected on the multiplexed pins. When this bit is reset to
0, these multiplexed pins become RxA1, TxA1 and RxS/
CTS1.
Bit 5 PB4-PB0 Select
When this bit is set to 1, parallel Port B bits 4 through 0 are
selected on the multiplexed pins. When this bit is reset to
0, these multiplexed pins take ASCI channel 0 functions.
Bit 4 DD ROM Emulator Mode Enable
OUT
When this bit is set to 1, the Z182 is in “ROM emulator
mode”. In this mode, bus direction for certain transaction
periods are set to the opposite direction to export internal
bus transactions outside the Z80182/Z8L182. This allows
the use of ROM emulators/logic analyzers for application
development (see Tables 12a and 12b).
Note: The word “Out” means that the Z182 data bus
direction is in output mode, “In” means input mode, and “Z”
means high impedance. DD_OUT stands for Data Direction
Out and is the status of the D4 bit in the System Configuration
Register (SCR).
Table 12a. Data Bus Direction (Z182 Bus Master)
I/O And Memory Transactions
I/O Write
I/O Read
I/O Write
I/O Read
Write
to On-Chip From On-Chip to Off-Chip From Off-Chip To
Peripherals Peripherals Peripherals Peripherals Memory
Read
From
Mode
Z80182
/Z8L182
Refresh Idle Mode
Z80182
Out
/Z8L182
Data Bus
(DD =0)
OUT
Z80182
Out
/Z8L182
Data Bus
(DD_OUT =1)
Z
Out
Out
Out
In
Out
In
Z
Z
In
Out
In
Z
Z
DS971820600
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