Z80182 Datasheet, PDF (66/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
Interrupt Vector Register (Continued)
Table 16. Interrupt Status Bits
Bits 3, 2, 1
Interrupt Request
000
NO IRQ
001
FCR or Tx OVRN IRQ
010
DLL/DLM IRQ
011
LCR IRQ*
100
MCR IRQ*
101
RBR IRQ
110
TTO IRQ
111
THR IRQ
Note: * The order of LCR and MCR does not follow that of the IE Register.
Bit 7 and Bit 6 XMIT Trigger MSB,LSB
This field determines the number of bytes available to read
in the transmitter FIFO before an interrupt occurs to the
MPU (Table 17).
Table 17. Transmitter Trigger Level
b7
b6
Level (# bytes)
0
0
1
0
1
4
1
0
8
1
1
14
Bit 0 0/Opcode (Read/Write)
This bit is always 0 when the VIS bit is 1. If the VIS bit is 0,
this bit reads back what was last written to it.
The Interrupt Vector Register serves both interrupt modes.
When the VIS bit is 0, the last value written to the register
can be read back. If the VIS bit is 1, and an interrupt is
pending, the value read is the last value written to the
upper nibble plus the status for the interrupt that is pending.
If no interrupt is pending, then the last value written to the
upper nibble plus the lower nibble is read from the register.
If the vector includes the status, then the lower four bits of
the vector change asynchronously depending on the
interrupting source. Since this vector changes
asynchronously, then the interrupt service routine to read
the IVEC register might read the source of the most recent
IRQ/INTACK cycle if that IRQ does not have its IUS set.
Bit 5 Receive Timeout Enable
This bit enables the Z80182/Z8L182 Receive Timeout
Timer that is used to emulate the four character timeout
delay that is specified by the 16550. If no read or write to
the RCVR FIFO has taken place and data bytes are
available, but are below the PC trigger level. If this timer
reaches zero, an interrupt is sent to the PC.
Bit 4 Transmitter Timeout Enable
This bit enables the Z80182/Z8L182 timer that is used to
interrupt the Z180 MPU if characters are available, but are
below the trigger level. The timer is enabled to count down
if this bit is 1 and the number of bytes is below the set
transmitter trigger level. The timer will timeout and interrupt
the MPU if no read or write to the XMIT FIFO takes place
within the timer interval.
Bit 3 Reserved. Program to zero.
D7 D6 D5 D4 D3 D2 D1 D0
0 00 00000
16450 MIMIC mode Enable
RTO Timeout Enhancement
TEMT Enable
Reserved for
Future Use
Always write and
read as 0
XMIT Timeout Enable
RCVR Timeout Enable
XMIT Trigger LSB
XMIT Trigger MSB
Figure 64. FIFO Status and Control Register
(Z180 MPU Read/Write, Address xxECH)
Bit 2 (Reset value = 0) TEMT/Double Buffer
When enabled the Tx buffer can hold one extra byte (2
bytes total in 16450 mode). (Do not enable in 16550
mode.)
TEMT Emulation
If character delay emulation is not used the TEMT bit is
automated. (Refer to page 26 for TEMT/Double Buffer
information.)
Bit 1 RTO Timeout Enhancement
(Reset value = 0) Setting this bit will enable the RTO
timeout to emulate the 16550 device. When enabling this
feature, the receive timeout timer will not begin counting
down until the character emulation timer for each byte of
data in the Rx FIFO has expired.
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DS971820600