Z80182 Datasheet, PDF (97/109 Pages) Zilog, Inc. – ZILOG INTELLIGENT PERIPHERAL CONTROLLER (ZIP™)

Zilog
PRELIMINARY
Z80182/Z8L182
ZILOG INTELLIGENT PERIPHERAL
Table D. Z85230 System Timing Table
No.
Symbol
Parameter
20 MHz
Min
Max
1
TdRxC(REQ)
/RxC to /W//REQ Valid
2
TdRxC(W)
/RxC to /Wait Inactive
3
TdRxC(SY)
/RxC to /SYNC Valid
4
TdRxC(INT)
/RxC to /INT Valid
5
TdTxC(REQ)
/TxC to /W//REQ Valid
13
18
13
18
9
13
15
22
8
12
6
TdTxC(W)
7
TdTxC(DRQ)
8
TdTxC(INT)
9
TdSY(INT)
10
TdExT(INT)
/TxC to /Wait Inactive
/TxC to /DTR//REQ Valid
/TxC to /INT Valid
/SYNC to /INT Valid
/DCD or /CTS to /INT Valid
Notes:
These AC parameters values are preliminary and subject to change without notice.
[1] Open-drain output, measured with open-drain test load.
[2] /RxC is /RTxC or /TRxC, whichever is supplying the receive clock.
[3] /TxC is /TRxC or /RTxC, whichever is supplying the transmit clock.
[4] Units equal to TcPc
8
15
7
11
9
14
2
6
3
9
Notes [4]
[2]
[1,2]
[2]
[1,2]
[3]
[1,3]
[3]
[1,3]
[1]
[1]
No. Symbol
1
TsPIA(RD)
2
ThPIA(RD)
3
TdWR_F(PIA)
4
T WR (PIA)
F
F
Table E. I/O Port Timing
Parameter
Port Data Input Setup to /RD Fall
Port Data Input Hold From /RD Rise
Port Data Output Delay From /WR Fall
Port Data Output Float From /WR Fall
Z8L182
20 MHz
Min
Max
20
0
60
0
Z80182
33 MHz
Min Max
20
0
60
0
No. Symbol
1
TsA(IORQf)
2
TsIOf(WRf)
3
TsIOf(RDf)
4
ThIOR(WR_R)
5
ThIOR(RD )
R
6
TdRDf(DO)
7
T_HRD_R(DO)
8
T_SD(WR_R)
9
THD(WR_R)
Table F. External Bus Master Timing
Parameter
Z8L182
20 MHz
Min
Max
Address to /IORQ Fall Setup
10
/IORQ Fall to /WR Fall Setup
0
/IORQ Fall to /RD Fall Setup
0
/IORQ Rise From /WR Rise Hold
0
/IORQ Rise From /RD Rise Hold
/RD Fall to Data Out Valid Delay
/RD Rise to Data Out Valid Hold
Data In to /WR Fall Setup
Data In From /WR Rise Hold
0
50
0
50
10
8
Z80182
33 MHz
Min Max
5
0
0
0
0
45
0
50
10
DS971820600
3-97